Method of manufacturing a semiconductor device

ABSTRACT

In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening. Because the upper width of the opening is larger than the lower width, no seam or void would be generated in the second polysilicon layer, therefore improving the electrical characteristics and reliability of the device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.11/149,702, filed on Jun. 9, 2005, now pending, which claims priorityunder 35 USC § 119 to Korean Patent Application No. 2004-49250, filed onJun. 29, 2004, the contents of which are incorporated herein byreference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing asemiconductor device. More particularly, the present invention relatesto a method of manufacturing a semiconductor device including aself-aligned polysilicon layer having no seam or void therein.

2. Description of the Related Art

Semiconductor devices are generally divided into volatile semiconductordevices, such as dynamic random access memory (DRAM) devices or staticrandom access memory (SRAM) devices, and non-volatile semiconductordevices like a read only memory (ROM) devices. Volatile semiconductordevices have a relatively high response speed; however, data storedtherein may be lost with the lapse of time. Although non-volatilesemiconductor devices permanently store data therein, such devices havea relatively low response speed.

Recently, non-volatile semiconductor devices such as flash memorydevices or electrically erasable and programmable ROM (EEPROM) deviceshave been widely used in various electronic apparatuses. In flash memorydevices, data may be electrically stored and/or read out from memorycells of the flash memory devices by employing either theFlower-Nordheim tunneling effect or hot carrier injection effect. Flashmemory devices are typically divided into a NAND type memory device anda NOR type memory device. In the NAND type memory device, a plurality ofcell transistors is serially connected to form unit strings and the unitstrings are connected in parallel to a bit line and a ground line. Inthe NOR type memory device, each of the cell transistors is electricallyconnected in parallel between a bit line and a ground line. Both havetheir respective advantages: the NAND type memory device may have arelatively high response speed, while the NOR type memory device has arelatively high integration.

Memory cells used in flash memory devices typically have a verticallystacked gate structure that includes a floating gate formed on a siliconsubstrate. The stacked gate structure generally has at least one tunneloxide layer or dielectric layer, and a control gate formed on or nearthe floating gate. In the memory cell of the NAND type memory device, aplurality of floating gates is formed in an active region having a lineshape. Here, the floating gates are intended to be exactly formed atpredetermined portions of the active region. However, due to decreasingdesign rules, the floating gates may not be precisely formed at thepredetermined portions of the active region due to the active region'sgreatly reduced size. That is, the critical dimensions of the floatinggate decrease much more quickly than the design rules for flash memorydevices as a whole.

To solve the above-mentioned problem, there has been developed a methodof forming a floating gate including a self-aligned polysilicon (SAP)layer. In this method, after an opening is formed through an isolationlayer, a polysilicon layer is formed to fill up the opening, therebyforming the floating gate. However, poor step coverage may cause thepolysilicon layer to not completely fill up the opening when theopening, thereby forming a seam in the polysilicon layer. This seamformation problem is further exacerbated by the fact that openingsformed through the isolation layer generally have an upper portionrelatively narrower than a lower portion thereof.

FIG. 1 is a cross sectional view illustrating a seam generated in apolysilicon layer for a floating gate of a conventional flash memorydevice.

As shown in FIG. 1, a seam 12 is inadvertently formed in a polysiliconlayer 10 when filling the opening formed through an isolation layer 15.This seam might not be completely removed in a subsequent process forforming a floating gate, therefore resulting in an undesired electricaleffect. That is, oxide may form in the seam 12 in a successive processthereby degrading the electrical characteristics of the flash memorydevice.

SUMMARY OF THE INVENTION

The present invention provides a method of manufacturing a semiconductordevice including a polysilicon layer without a seam or a void therein.

The present invention also provides a method of manufacturing asemiconductor device including a polysilicon layer to improve electricalcharacteristics and reliability thereof.

In accordance with one aspect of the present invention, there isprovided a method of manufacturing a semiconductor device. In themethod, an isolation pattern is formed on a substrate. The isolationpattern includes an opening that exposes a portion of the substrate. Apreliminary polysilicon layer is formed on the substrate and theisolation pattern to partially fill up the opening. After a sacrificiallayer is formed on the preliminary polysilicon layer, the sacrificiallayer is partially etched to expose a portion of the preliminarypolysilicon layer formed on a shoulder portion of the isolation pattern.A first polysilicon layer is formed by etching the exposed portion ofthe preliminary polysilicon layer to enlarge an upper width of theopening. After the etched sacrificial layer is removed, a secondpolysilicon layer is formed on the first polysilicon layer to fill upthe enlarged opening.

In an exemplary embodiment of the present invention, the sacrificiallayer may have a first thickness from a portion of the preliminarypolysilicon layer positioned on a bottom face of the opening, and mayhave a second thickness substantially thinner than the first thicknessfrom a portion of the preliminary polysilicon layer positioned on asidewall of the opening. The sacrificial layer may be formed by a highdensity plasma chemical vapor deposition (HDP-CVD) process.

In an exemplary embodiment of the present invention, the sacrificiallayer may have a first thickness from a portion of the preliminarypolysilicon layer positioned on a bottom face of the opening, and mayhave a second thickness substantially thinner than the first thicknessfrom a portion of the preliminary polysilicon layer positioned on theisolation pattern. The sacrificial layer may include undoped silicateglass (USG), boro-phosphor silicate glass (BPSG), flowable oxide (FOX),etc.

In an exemplary embodiment of the present invention, the sacrificiallayer may be partially etched and then removed by wet etching processes.Each of the wet etching processes may be performed using an etchingsolution including a diluted hydrogen fluoride (HF) solution or an LALsolution.

In an exemplary embodiment of the present invention, the firstpolysilicon layer may be formed by a wet etching process using anetching solution having an etching selectivity of above about 1:10between the sacrificial layer and the preliminary polysilicon layer. Theetching solution may include ammonium hydroxide (NH₄OH), hydrogenperoxide (H₂O₂) and deionized water with a volume ratio of about 3 toabout 10:about 1:about 60 to about 200.

In accordance with another aspect of the present invention, there isprovided a method of manufacturing a semiconductor device. In themethod, after a mask pattern is formed on a substrate, trenches areformed on the substrate by etching the substrate using the mask patternas an etching mask. Isolation layers are formed to fill up the trenches,and then an opening is formed by removing the mask pattern to expose anactive region of the substrate between the isolation layers. A firstdielectric layer is formed on the exposed active region. A preliminarypolysilicon layer is formed on the first dielectric layer and theisolation layers to partially fill up the opening. A sacrificial layeris formed on the preliminary polysilicon layer. The sacrificial layerhas a first thickness from a portion of the preliminary polysiliconlayer positioned on a bottom face of the opening, and has a secondthickness substantially thinner than the first thickness from a portionof the preliminary polysilicon layer positioned on a sidewall of theopening. The sacrificial layer is partially etched to expose a portionof the preliminary polysilicon layer formed on a shoulder portion of theopening. A first polysilicon layer is formed by etching the exposedportion of the preliminary polysilicon layer to enlarge an upper widthof the opening. Then, the etched sacrificial layer is removed. After asecond polysilicon layer is formed on the first polysilicon layer tofill up the enlarged opening, a floating gate is formed by removing thesecond and first polysilicon layers until the isolation layers areexposed.

In an exemplary embodiment of the present invention, after the isolationlayers are partially removed to partially expose a sidewall of thefloating gate, a second dielectric layer is formed on the floating gate.Then, a control gate is formed on the second dielectric layer.

In accordance with another aspect of the present invention, there isprovided a method of manufacturing a semiconductor device. In themethod, a mask pattern is formed on a substrate, and then trenches areformed on the substrate by etching the substrate using the mask patternas an etching mask. After isolation layers are formed to fill up thetrenches, an opening is formed by removing the mask pattern to expose anactive region of the substrate between the isolation layers. A firstdielectric layer is formed on the exposed active region. A preliminarypolysilicon layer is formed on the first dielectric layer and theisolation layers to partially fill up the opening. A sacrificial layeris formed on the preliminary polysilicon layer. The sacrificial layerhas a first thickness from a portion of the preliminary polysiliconlayer positioned on a bottom face of the opening, and has a secondthickness substantially thinner than the first thickness from a portionof the preliminary polysilicon layer positioned on the isolation layers.The sacrificial layer is partially etched to expose portions of thepreliminary polysilicon layer formed on the isolation layer and ashoulder portion of the opening. A first polysilicon layer is formed byetching the exposed portions of the preliminary polysilicon layer toenlarge an upper width of the opening. After the etched sacrificiallayer is removed, a second polysilicon layer is formed on the firstpolysilicon layer to fill up the enlarged opening. Then, a floating gateis formed by removing the second and first polysilicon layers until theisolation layers are exposed.

According to the present invention, no seam or void is generated in apolysilicon layer for a floating gate while the polysilicon layer isformed in a self-aligned process relative to an isolation layer formedon a substrate. Therefore, a semiconductor device including thepolysilicon layer such as a flash memory device may have improvedelectrical characteristics and reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become readily apparent by reference to the following detaileddescription when considered in conjunction with the accompanyingdrawings wherein:

FIG. 1 is a cross sectional view illustrating a seam generated in apolysilicon layer for floating gate of a conventional flash memorydevice;

FIGS. 2 to 13 are cross sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with an exemplaryembodiment of the present invention; and

FIGS. 14 to 17 are cross sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with an exemplaryembodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the exemplary embodiments set forth herein; rather, these embodimentsare provided so that this disclosure will be through and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. Like reference numerals refer to similar oridentical elements throughout. It will be understood that when anelement such as a layer, region or substrate is referred to as being“on” or “onto” another element, it can be directly on the other elementor intervening elements may also be present.

FIGS. 2 to 13 are cross sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with an exemplaryembodiment of the present invention.

Referring to FIG. 2, after a buffer layer is formed on a substrate 100,a first insulation layer is formed on the buffer layer. The buffer layermay be formed using an oxide such as silicon oxide, and the substrate100 may include a silicon wafer. The first insulation layer may beformed using a material that has an etching selectivity relative to thebuffer layer. For example, the first insulation layer includes a nitridesuch as silicon nitride.

After a photoresist film is formed on the first insulation layer, thephotoresist film is exposed and developed to thereby form a photoresistpattern (not shown) on the first insulation layer.

The first insulation layer and the buffer layer are partially etchedusing the photoresist pattern as an etching mask, thereby forming a hardmask pattern 102 on the substrate 100. The hard mask pattern 102includes a buffer layer pattern 102 a formed on the substrate 100 and afirst insulation layer pattern 102 b formed on the buffer layer pattern102 a. The hard mask pattern 102 selectively exposes a field region ofthe substrate 100. After the hard mask pattern 102 is formed on thesubstrate 100, the photoresist pattern is removed from the hard maskpattern 102 by an ashing process and/or a stripping process.Alternatively, the photoresist pattern may be consumed in an etchingprocess for forming a trench 108 (see FIG. 3) without performing anyadditional process.

The hard mask pattern 102 serves as an etching mask in an isolationprocess for forming the trench 108 so that the hard mask pattern 102defines an active region of the substrate 100 where a floating gate 123(see FIG. 12) is positioned. The hard mask pattern 102 may have athickness substantially thicker than that of the floating gate 123.However, a second insulation layer may not completely fill up the trench108 if the hard mask pattern 102 is too thick compared to the floatinggate. Therefore, the hard mask pattern 102 may have a thickness about 5%to about 15% thicker than that of the floating gate 123. When the hardmask pattern 102 is employed for defining the active region where thefloating gate 123 is formed, the hard mask pattern 102 may have athickness relatively thicker than that of a conventional hard maskpattern used only as an etching mask for forming a trench.

In an exemplary embodiment of the present invention, the buffer layerand the first insulation layer may be etched by a dry etching process.When the buffer layer pattern 102 a and the first insulation layerpattern 102 b are formed through the dry etching process, sidewalls ofthe buffer and the first insulation layer patterns 102 a and 102 b mayhave slopes with predetermined angles. In other words, the hard maskpattern 102 may have a lower portion relatively wider than an upperportion thereof. Hence, an area of the substrate 100 masked by the hardmask pattern 102 may be relatively wider than an area of the substrate100 masked by the photoresist pattern. When the substrate 100 ispartially etched using the hard mask pattern 102 having theabove-described structure, the trench 108 may have a width relativelynarrower than that of an area of the hard mask pattern 102 exposed bythe photoresist pattern.

An oxide layer (not shown) is formed on the substrate 100 exposed by thehard mask pattern 102. The oxide layer may be formed by a thermaloxidation process or a chemical vapor deposition (CVD) process. Forexample, the oxide layer includes silicon oxide. When the oxide layer isformed through the thermal oxidation process, silicon oxide layers areformed on portions of the substrate 100 making contact with lower edgeportions of the hard mask pattern 102 in accordance with the consumptionof the substrate 100 due to bird's beak phenomenon. As the substrate 100is partially consumed, the portions of the substrate 100 contacting thelower edge portions of the hard mask pattern 102 may have round shapes.In one embodiment of the present invention, the oxide layer may not beformed on the substrate 100 to simplify the method of manufacturing thesemiconductor device.

Referring to FIG. 3, the trench 108 is formed by partially etching thesubstrate 100 using the hard mask pattern 102 as an etching mask. Whenthe trench 108 is formed on the substrate 108, the field region and theactive region are defined on the substrate 100. That is, the fieldregion corresponds to the trench 108, whereas the active regioncorresponds to a portion of the substrate 100 where the hard maskpattern 102 is positioned.

A sidewall oxide layer (not shown) is formed on a sidewall of the trench108 by a thermal oxidation process or a CVD process. The sidewall oxidelayer is formed to cure the damage to the substrate 100 generated in theetching process of forming the trench 108. The sidewall oxide layer mayhave a thickness of about 30 Å to about 200 Å. In one embodiment of thepresent invention, an additional oxide layer may be formed on thesidewall oxide layer by a CVD process using middle temperature oxide(MTO). The additional oxide layer may prevents the damage to thesubstrate 100 generated in a successive process of forming the secondinsulation layer that fills up the trench 108.

Referring to FIG. 4, the second insulation layer is formed on thesubstrate 100 to fill up the trench 108 and to cover the hard maskpattern 102. The second insulation layer may be formed using oxide by ahigh density plasma chemical vapor deposition (HDP-CVD) process(hereinafter, referred to as HDP-CVD oxide). In the HDP-CVD process, thesecond insulation layer is formed by simultaneously performing adepositing step and a sputtering step. Thus, the second insulation layermay have a dense structure and a high electrical insulation property sothat the second insulation layer may be advantageously used as anisolation layer 110 of the semiconductor device.

An upper portion of the second insulation layer is removed by aplanarization process until the hard mask pattern 102 is exposed,thereby forming the isolation layer 110 in the trench 108. The secondinsulation layer may be partially removed by a chemical mechanicalpolishing (CMP) process, an etch back process or a combination processof CMP and etch back.

Referring to FIG. 5, the hard mask pattern 102 is removed from thesubstrate 100 by an etching process. When the hard mask pattern 102 isremoved, the active region of the substrate 100 is exposed. The hardmask pattern 102 may be etched by a wet etching process. In the wetetching process, the hard mask pattern 102 is etched using an etchingsolution that mainly etches a nitride. Here, the etching solution mayinclude phosphoric acid (H₃PO₄). When the first insulation layer pattern102 b including nitride is removed using the etching solution includingphosphoric acid, the buffer layer pattern 102 a of oxide may besimultaneously removed from the substrate 100 without any additionalprocess for etching the buffer layer pattern 102 a.

When the hard mask pattern 102 is removed, an opening 112 is formed at aposition where the hard mask 102 is located. That is, the opening 112exposing the active region of the substrate 100 is formed between theisolation layers 110. Here, an upper face of the isolation layer 110 issubstantially higher than that of the active region. Since the lowerportion of the hard mask pattern 102 is relatively wider than the upperportion thereof a lower portion of the opening 112 is also relativelywider than an upper portion of the opening 112.

Referring to FIG. 6, a first dielectric layer 114 is formed on theactive region. The first dielectric layer 114 may include an oxide suchas silicon oxide. Further, the first dielectric layer 114 may be formedusing a thermal oxidation process or a CVD process. The first dielectriclayer 114 serves as a tunnel oxide layer of the semiconductor device.

A first preliminary polysilicon layer 116 is formed on the firstdielectric layer 114, a sidewall of the isolation layer 110 and an upperface of the isolation layer 110. Thus, the opening 112 is partiallyfilled with the first preliminary polysilicon layer 116. The firstpreliminary polysilicon layer 116 may be formed using a low pressurechemical vapor deposition (LPCVD) process. Impurities may be doped intothe first preliminary polysilicon layer 116 by a diffusion process, anion implantation process or an in-situ doping process.

Because the first preliminary polysilicon layer 116 has good stepcoverage, the first preliminary polysilicon layer 116 may have athickness substantially smaller than a half of a width of the upperportion of the opening 112 so that the first preliminary polysiliconlayer 116 partially fills up the opening 112. Preferably, the firstpreliminary polysilicon layer 116 may have a thickness substantiallysmaller than about one-third of the width of the upper portion of theopening 112.

Referring to FIG. 7, a sacrificial layer 118 is formed on the firstpreliminary polysilicon layer 116. The sacrificial layer 118 protects aportion of the first preliminary polysilicon layer 116 in a successiveetching process. The sacrificial layer 118 may include an oxide such asHDP-CVD oxide. The sacrificial layer 118 has a first thickness from abottom face of the opening 112 and a second thickness from the sidewallof the opening 112. The second thickness of the sacrificial layer 118 isrelatively thinner than the first thickness of the sacrificial layer118. When the sacrificial layer 118 is formed on the first preliminarypolysilicon layer 116, approximately half of the opening 112 is filledwith the sacrificial layer 118.

Referring to FIG. 8, the sacrificial layer 118 is partially etched tothereby form first and second sacrificial layer patterns 118 a and 118b. The first sacrificial layer pattern 118 a is formed in the opening112 and the second sacrificial layer pattern 118 b is positioned on theisolation layer 110. That is, the first sacrificial layer pattern 118 ais formed on a portion of the first preliminary polysilicon layer 116positioned on the bottom face of the opening 112, whereas the secondsacrificial layer pattern 118 b is formed on a portion of the firstpreliminary polysilicon layer 116 positioned on the isolation layer 110.When the first and second sacrificial layer patterns 118 a and 118 b areformed, a portion A of the first preliminary polysilicon layer 116positioned on and around a shoulder portion of the isolation layer 110is exposed.

The first and the second sacrificial layer patterns 118 a and 118 b maybe formed by a wet etching process using an etching solution. Theetching solution may include a diluted hydrogen fluoride (HF) solutionor an LAL solution. The LAL solution typically includes ammoniumfluoride (NH₃F), hydrogen fluoride and deionized water (H₂O). In the wetetching process for partially etching the sacrificial layer 118,processing time of the etching process is properly controlledconsidering an etching rate of the sacrificial layer 118. Thus, thefirst and the second sacrificial layer patterns 118 a and 118 b areformed on the first preliminary polysilicon layer 116 so that theportion A of the first preliminary polysilicon layer 116 on the shoulderportion of the isolation layer 110 is exposed.

Referring to FIG. 9, the exposed portion A of the first preliminarypolysilicon layer 116 is partially or completely etched to form a firstpolysilicon layer 120 on the first dielectric layer 114, the upper faceof the field isolation layer 110 and the sidewall of the isolation layer110. Since the exposed portion of the first preliminary polysiliconlayer 116 is partially or fully etched as shown “B”, the width of theupper portion of the opening 112 is increased by an etched thickness ofthe exposed portion A of the first preliminary polysilicon layer 116.That is, although the exposed portion A of the first preliminarypolysilicon layer 116 is partially etched as shown “B” in FIG. 9, theexposed portion A of the first preliminary polysilicon layer 116 may befully etched to increase the width of the upper portion of the opening112. The first polysilicon layer 120 may be formed by a wet etchingprocess. When the first preliminary polysilicon layer 116 is etched by adry etching process, the first preliminary polysilicon layer 116 may notbe properly etched because the second sacrificial layer pattern 118 b ispositioned on the isolation layer 110. Further, the dry etching processmay cause damage to the first dielectric layer 114 formed beneath thefirst preliminary polysilicon layer 116.

In the wet etching process of etching the first preliminary polysiliconlayer 116, an etching solution having an etching selectivity of morethan about 1:10 between the sacrificial layer patterns 118 a and 118 band the first preliminary polysilicon layer 116. When the sacrificiallayer patterns 118 a and 118 b are etched together with the firstpreliminary polysilicon layer 116, the first sacrificial layer pattern118 a may not cover the portion of the first preliminary polysiliconlayer 116 positioned on the first dielectric layer 114, thereby causingdamage to the first dielectric layer 114. The etching solution mayinclude ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂) anddeionized water. For example, the etching solution includes an NSC-1(new standard cleaning-1) solution. The NSC-1 solution contains ammoniumhydroxide, hydrogen peroxide and deionized water with a volume ratio ofabout 3 to about 10:about 1:about 60 to about 200. Preferably, theetching solution includes the NCS-1 solution that contains ammoniumhydroxide, hydrogen peroxide and deionized water with a volume ratio ofabout 4:about 1:about 95. The wet etching process may be performed at atemperature of about 70 to about 90° C. Preferably, the exposed portionA of the first preliminary polysilicon layer 116 may be partially orcompletely etched at a temperature of about 80° C.

When the wet etching process of etching the exposed portion A of thefirst preliminary polysilicon layer 116 is carried out at thetemperature of about 80° C. using the etching solution including theNCS-1 solution that contains ammonium hydroxide, hydrogen peroxide anddeionized water with a volume ratio of about 4:about 1:about 95, anetching selectivity of the first preliminary polysilicon layer 116relative to the sacrificial layer patterns 118 a and 118 b is about12.5:1. For example, an etching rate of the first preliminarypolysilicon layer 116 is about 31.5 Å/min, and an etching rate of thesacrificial layer patterns 118 a and 118 b is about 2.5 Å/min.

Referring to FIG. 10, the first and the second sacrificial layerpatterns 118 a and 118 b are removed to complete the first polysiliconlayer 120. Since the exposed portion A of the first preliminarypolysilicon layer 116 is partially or fully etched as describe above,the opening 112 has the upper portion having the increased width by theetched thickness of the first preliminary polysilicon layer 116. Hence,the upper portion of the opening 112 has a width substantially widerthan that of the lower portion thereof. In other words, the sidewall ofthe opening 112 has a positive slope relative to a vertical line to thesubstrate 100.

The first and the second sacrificial layer patterns 118 a and 118 b maybe removed from the first polysilicon layer 120 by a wet etchingprocess. In the wet etching process, an etching solution for etching thesacrificial layer patterns 118 a and 118 b may include a dilutedhydrogen fluoride solution or an LAL solution.

Referring to FIG. 11, a second polysilicon layer 122 is formed on thefirst polysilicon layer 120 to completely fill up the opening 112. Whenthe second polysilicon layer 122 fills up the opening 112, no seam orvoid is generated in the second polysilicon layer 122 because theopening 112 has the upper portion having the increased width.

Referring to FIG. 12, the first and the second polysilicon layer 120 and122 are partially removed by a planarization process until the isolationlayer 110 is exposed, thereby forming the floating gate 123 in theactive region of the substrate 100. The first and the second polysiliconlayer 120 and 122 may be partially removed by a CMP process, an etchback process or a combination process of CMP or an etch back.

The floating gate 123 includes a first polysilicon layer pattern 120 aand a second polysilicon layer pattern 122 a. The first polysiliconlayer pattern 120 a is formed on the first dielectric layer 114 and thesidewall of the opening 112, and the second polysilicon layer pattern122 a is positioned on the first polysilicon layer pattern 120 a to fillup the opening 112.

Referring to FIG. 13, an upper portion of the isolation layer 110 isetched by a wet etching process for a dry etching process to therebyexpose a sidewall of the floating gate 123. Here, an upper face of theetched isolation layer 110 is substantially higher than a bottom face ofthe floating gate 123. That is, the sidewall of the floating gate 123 ispartially exposed after the isolation layer 110 is partially removed.Thus, the first dielectric layer 114 is not exposed after the etchingprocess of the isolation layer 110. As a result, the first dielectriclayer 114 may not be damaged in the etching process of the isolationlayer 110 and/or successive manufacturing processes.

A second dielectric layer 124 is formed on the etched isolation layer110 and the floating gate 123. The second dielectric layer 124 may beformed using a material having a high dielectric constant.Alternatively, the second dielectric layer 124 may have anoxide/nitride/oxide (ONO) structure that includes a lower oxide film, anitride film and an upper oxide film sequentially formed on the floatinggate 123.

A conductive layer 126 is formed on the second dielectric layer 124. Theconductive layer 126 may be formed using a conductive material such asdoped polysilicon, metal or a conductive metal nitride. Alternatively,the conductive layer 126 may have a polyside structure that includes adoped polysilicon film and a metal silicide film.

The conductive layer 126 is patterned by a typical photolithographyprocess to thereby form a control gate (not shown) on the seconddielectric layer 124. Then, the second dielectric layer 124, thefloating gate 123 and the first dielectric layer 114 are partiallyetched, thereby forming a gate structure of the semiconductor device onthe substrate 100.

When source/drain regions (not shown) are formed at portions of activeregion adjacent to the gate structure by an ion implantation process,the semiconductor device such as a flash memory device is completed onthe substrate 100.

FIGS. 14 to 17 are cross sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with an exemplaryembodiment of the present invention.

Referring to FIG. 14, after a buffer layer is formed on a substrate 200,a first insulation layer is formed on the buffer layer. The buffer layermay be formed using an oxide such as silicon oxide, and the firstinsulation layer may be formed using a nitride such as silicon nitride.

After a photoresist pattern is formed on the first insulation layer, thefirst insulation layer and the buffer layer are partially etched usingthe photoresist pattern as an etching mask so that a hard mask patternis formed on the substrate 200. The hard mask pattern includes a bufferlayer pattern and a first insulation layer pattern successively formedon the substrate 200. The hard mask pattern selectively exposes a fieldregion of the substrate 200.

A trench is formed by partially etching the substrate 200 using the hardmask pattern as an etching mask so that the field region and the activeregion are defined on the substrate 200.

A second insulation layer is formed on the substrate 200 to fill up thetrench and to cover the hard mask pattern. The second insulation layermay be formed using oxide by an HDP-CVD process.

An upper portion of the second insulation layer is removed by aplanarization process until the hard mask pattern is exposed, so that anisolation layer 210 is formed in the trench. The second insulation layermay be partially removed by a CMP process, an etch back process or acombination process of CMP and etch back.

The hard mask pattern is removed from the substrate 200 by an etchingprocess so that the active region of the substrate 200 is exposed. Whenthe hard mask pattern is removed, an opening is formed at a positionwhere the hard mask is positioned. The opening exposing the activeregion of the substrate 200 is formed between the isolation layers 210substantially higher than the active region.

A first dielectric layer 214 is formed on the active region using anoxide such as silicon oxide by a thermal oxidation process or a CVDprocess. The first dielectric layer 214 may serve as a tunnel oxidelayer of the semiconductor device.

A first preliminary polysilicon layer 216 is formed on the firstdielectric layer 214, a sidewall of the isolation layer 210 and an upperface of the isolation layer 210. Thus, the opening is partially filledwith the first preliminary polysilicon layer 216. The first preliminarypolysilicon layer 216 may be formed using an LPCVD process.Additionally, impurities may be doped into the first preliminarypolysilicon layer 216 by a diffusion process, an ion implantationprocess or an in-situ doping process.

A sacrificial layer 250 is formed on the first preliminary polysiliconlayer 216 to fill up the opening. The sacrificial layer 250 may beformed using an oxide such as undoped silicate glass (USG),boro-phosphor silicate glass (BPSG), flowable oxide (FOX), etc. Thesacrificial layer 250 has a first thickness from a bottom face of theopening and a second thickness from the sidewall of the opening. Thesecond thickness of the sacrificial layer 250 is relatively thinner thanthe first thickness of the sacrificial layer 250.

Referring to FIG. 15, the sacrificial layer 250 is partially etched tothereby form a sacrificial layer pattern 250 a in the opening. That is,the sacrificial layer pattern 250 a is formed on a portion of the firstpreliminary polysilicon layer 216 positioned on the bottom face of theopening.

The sacrificial layer 250 may be partially etched by a wet etchingprocess using an etching solution. The etching solution may include adiluted hydrogen fluoride solution or an LAL solution. Alternatively,the sacrificial layer pattern 250 may be formed in the opening by a dryetching process.

When the sacrificial layer pattern 250 a is formed in the opening,portions of the first preliminary polysilicon layer 216 are exposed.That is, portions of the first preliminary polysilicon layer 216positioned on the isolation layer 210 and an upper sidewall of theopening are exposed in accordance with partial etching of thesacrificial layer 250.

Referring to FIG. 16, the exposed portions of the first preliminarypolysilicon layer 216 are removed to thereby form a first polysiliconlayer 240 on the first dielectric layer 214 and the sidewall of theisolation layer 210. Namely, the first polysilicon layer 240 is formed aportion of the sidewall of the opening. The first polysilicon layer 240may be formed by a wet etching process. When the first preliminarypolysilicon layer 216 is etched by a dry etching process using a plasma,the first preliminary polysilicon layer 216 may not be properly etchedbecause the sacrificial layer pattern 250 a is formed on the isolationlayer 210. Additionally, the plasma used in the dry etching process maycause damage to the first dielectric layer 214 formed beneath the firstpreliminary polysilicon layer 216.

In the wet etching process of etching the first preliminary polysiliconlayer 216, an etching solution having an etching selectivity of morethan about 1:10 between the sacrificial layer pattern 250 a and thefirst preliminary polysilicon layer 216.

Referring to FIG. 17, the sacrificial layer pattern 250 a is completelyremoved to expose the first polysilicon layer 240. Because the firstpolysilicon layer 240 is formed on the bottom face and a lower sidewallof the opening, the opening may have a reduced aspect ratio. Inaddition, a width of a lower portion of the opening may be reduced by athickness of the first polysilicon layer 240. That is, the opening hasan upper portion having a width relatively wider than the lower portionthereof by the thickness of the first polysilicon layer 240.

The sacrificial layer pattern 250 a may be removed from the firstpolysilicon layer 240 by a wet etching process. In the wet etchingprocess, an etching solution for etching the sacrificial layer pattern250 a may include a diluted hydrogen fluoride solution or an LALsolution.

A second polysilicon layer 242 is formed on the first polysilicon layer240 and isolation layer 210 to completely fill up the opening. When thesecond polysilicon layer 242 fills up the opening, no seam or void isgenerated in the second polysilicon layer 242 because the opening hasthe upper portion having the increased width in accordance withformation of the first polysilicon layer 240.

The second polysilicon layer 242 is partially removed by a planarizationprocess until the isolation layer 210 is exposed so that a floating gateis formed in the active region of the substrate 200. The secondpolysilicon layer 242 may be partially removed by a CMP process, an etchback process or a combination process of CMP or an etch back.

The floating gate includes a first polysilicon layer pattern and asecond polysilicon layer pattern. The first polysilicon layer pattern isformed on the first dielectric layer 214 and the lower sidewall of theopening, and the second polysilicon layer pattern is positioned on thefirst polysilicon layer pattern to fill up the opening.

After an upper portion of the isolation layer 210 is etched to therebyexpose a sidewall of the floating gate, a second dielectric layer isformed on the etched isolation layer 210 and the floating gate.

A conductive layer is formed on the second dielectric layer, and thenthe conductive layer is patterned to thereby form a control gate on thesecond dielectric layer. After the second dielectric layer, the floatinggate and the first dielectric layer 214 are partially etched to form agate structure of the semiconductor device on the substrate 200,source/drain regions are formed at portions of active region adjacent tothe gate structure by an ion implantation process. As a result, thesemiconductor device such as a flash memory device is completed on thesubstrate 200.

According to the present invention, no seam or void is generated in apolysilicon layer for a floating gate while the polysilicon layer isformed in a self-aligned process relative to an isolation layer formedon a substrate. Therefore, a semiconductor device including thepolysilicon layer such as a flash memory device may have improvedelectrical characteristics and reliability.

Having thus described exemplary embodiments of the present invention, itis to be understood that the invention defined by the appended claims isnot to be limited by particular details set forth in the abovedescription as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof as hereinafter claimed.

1. A floating gate structure of a semiconductor device comprising: anouter polysilicon layer having an opening formed therein; and an innerpolysilicon layer with at least a portion of the inner polysilicon layerformed within the opening, the inner polysilicon layer having a lowerportion within the opening that is narrower than an upper portion. 2.The floating gate structure of claim 1, further comprising a firstdielectric layer formed over the top of the floating gate structure. 3.The floating gate structure of claim 2, further comprising a seconddielectric layer interposed between an active region of a substrate andthe outer polysilicon layer.
 4. The floating gate structure of claim 3,wherein the first dielectric layer is spaced from the second dielectriclayer.